Recently, a customer contacted me about the possibility of "fixing" their design from the standpoint of EMC. The board may function perfectly, but it won't pass most tests, including Conductive Immunity, Radiated Immunity, Radiated Emission, and Conductive Emission.
Some people may think a ground/Vdd plane is necessary for controlled impedance, but it is not necessary in all cases. The assumption you are making is wrong, you are taking a lot of risks by doing this. Unless you have a power plane, there is a good chance that you will fail to pass not just radiated emission, but also conductive and radiated immunity tests.
The fact that you can fail conductive immunity may surprise you, but I have seen this mistake so many times that I decided to write something about it since I have seen it so many times.
I have made some drawings for you to see. Let's take a look at them.
As you can see in the first drawing there is a signal generator connected to a PCB with a single capacitor (simple two-layer board). In accordance with the second drawing, we have the same setup, except that there is also a power plane connected to the capacitor in this drawing.
A spectrometer is connected to both outputs of the amplifiers so that they can be analyzed. In addition, we are keeping an eye on the entire spectrum, ranging from 9 kHz to 1 GHz, in real-time.
The question is, what is the expected impedance (rejection) in both cases?
When we consider the first case (no power plane), I expect that at the lower frequencies, we will see a "behaviour" similar to that of a capacitor. As soon as the parasitic inducer kicks in, the behaviour will resemble that of an inducer because the parasite has been induced. At higher frequencies, there is no RF rejection, which means we will not experience any RF interference. There is a difference between "high frequency" and "low frequency". For example, for X7R 0603 capacitors, it may resonate at a frequency less than 10 MHz or even a fraction of that frequency.
Since we have a nice place at Vdd/GND in the second case, we have to see if we can imagine that we have an almost perfect plane capacitor Cp parallel to C. It is likely that Cp will also resonate, but at a much higher frequency than C. This would be around 300-500 MHz.
The result of this will be an improvement in noise rejection across a wider range of spectrums, as a result!
There is also a thing to observe in a design when we have a two-layer board, that is the equivalent series inductance will be significantly higher than the same inductance (on the same capacitor) when we have a plane, which means that fr1 supersedes fr2. Due to this, even in the range of 150kHz-30MHz, there is a much higher likelihood of getting problems. As a result, you will also fail the CI test!
So, be careful, today you really need to be an RF engineer if you want to pass EMC.
Enjoy your design!
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