The following tips may be helpful if you're designing a solution that uses a 10/100 LAN Ethernet port.
Some very common Ethernet PHY (sometimes) causes a particular issue at 1GHz, I've seen the same problem at 250 MHz and 500 MHz, but 1GHz is the most problematic, if you don't know what to do, because it could mean a redesign, with the loss of a few months in your design cycle and extra EMC testing. However if you know wjat to do the solution is very easy.
I have outlined the main players in the drawing below.
On the left, we have an insulation transformer with integrated common mode filter, and on the right, we have an Ethernet signal, which may go to the LAN chip or directly to the microcontroller (if it has a built-in Ethernet PHY).
Figure 1 showing the main player of this issue.
Ethernet PHYs are among the most noisy chips you may have on your board.
It is possible that the signal on the "PHY" side will carry some high frequency harmonics that, if left unattended, can cause some EMC problems.
As I'm not going to discuss the emission path in this post (because there are two of them and it would result in a lomg regression), I will only discuss a solution I use in all my designs to pass EMC.
The high frequency harmonics are always on a track that is eventually connected to a cable. An RF emission can result from that track. I minimize this risk by preventing all unwanted high frequency signals from using the cable as an antenna.
In what ways can we accomplish this?
We need to close the loop as soon as possible. We will place 10 - 20 pF capacitors on the track we believe may cause problems.
Therefore, the circuit from figure 1 is as follows:
Figure 2. a simple way to avoid the 1GHz Ethernet Emission
4 capacitors (between 10 and 20 pF) have been added to Figure 2. High frequency signals from the PHY find a low path impedance through the capacitors and return to the PHY.
It has worked for me more than once to solve the 1GHz Ethernet emissions.
In Figure 2 there is still one track where a high Frequency emission may arrive to the transformer and is the signal I called above ETH_3V3.
In this case the emission maybe created by your DCDC converter.
What I do to my design is to add a small ferrite in series to the 3.3V.
Now the circuit has finally become:
Figure 3. with the addition of a 0603 ferrite to minimize emission from the power supply
As we can see, EMC is really not black magic. once you understand the emission path you can find a solution.
Here's a little note:
Around 250 MHz, this solution may not work. If you are experiencing problems in that range, you are probably using some MII flavour interface such as GMII or RMII. Add a 22 ohm resistor on the clock and the data, and you will see the emission disappear.
I hope you enjoyed!
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