As part of my job, I have been analyzing PCB layouts that have been designed by third parties. Whenever I do this, it is interesting to see what typical mistakes people make when they are doing this. As an example, for some reason, when there is a differential signal, such as USB, RS485, etc., people tend to be more relaxed, and they are more inclined to ignore the basic EMC EMI rules, thinking that since the signal is a differential signal, errors tend to be more forgivable. Unfortunately, this is not the case. It is crucial that you pay attention to all the details when you are routing a critical signals. The attention to detail is sometimes what makes the difference between a prototype that works and a prototype that does not work.
As an example, let us take a look at what may occur when a differential pair is routed over a plane split in order to see what might happen.
As a preliminary step, let's observe how differential signals are routed above a nice return plane in order to see how their current flows when they are routed above it. In order to achieve this, let us take a closer look at FIG.1 below.
FIG.1 differential trace over a single reference plane.
We'll call i+ i- the forward current on differential traces + -.
When it comes to signal integrity (SI), each trace has to be treated as a single-ended high-speed trace for the purposes of SI (signal integrity).
As an example, let's take a look at the upper trace and analyze it first.
In the reference plane below the signal, a current return r+ is created as the upper case (let's call this current i+) moves over the trace.
On the lower trace, we can make the same observation. When a current i- moves on this trace, a return current r- is created in the reference plane.
Okay, we've got 2 traces with controlled impedance and minimized return current loops. As we know this is the ideal scenario from EMC and EMI point of view.
Now let's imagine we have routed those traces over 2 different power plane, e.g. 1.8V and 2.5V
Can you tell me what's going to happen to the return current r+ r-?
Figure 2 shows that the current return r+ will divert from its normal path below the upper trace and move below the lower trace.
FIG.2 differential trace over a split plane
What does that mean? Is it possible to have EMC EMI problems?
Sure, we can.
A loop current is formed by the currents i+,r+,i-,r-.
There's a chance this current loop will create a magnetic field strong enough to cause cross talk, emissions, etc.
Here's what I expect the track impedance to look like the one I drawn in figure 2. An uncontrolled impedance mismatch between the 2 planes.
How do we fix that?
EMI and EMC-wise, this is the best option for you if you can avoid routing the trace above two split planes.
In case you can't, I use stitching capacitors between planes as shown in FIG.3
FIG. 3 how we can reduce the emissions on differential trace over a split plane (just one capacitor is shown. Ideally you need one on each side of each trace.)
I've shown you above how a stitching capacitor will help the r+ r- current flow in the right direction and reduce the loop current.
Here's what we've got with the stitching capacitor
The current loop has been reduced
Reduced Z's increment
The loop antenna reduced emissions
Reduced crosstalk.
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