When we place our bypass capacitors on a PCB, there are several factors that may affect the series inductance of the capacitor ESL when it is placed on the board. What can we do in order to minimize it during the routing of our PCB? Do you consider the footprint of the capacitor when you select the capacitor? Yes, there are a few things that can be done in order to solve this problem. The first thing we need to do is look at the footprint. A general rule of thumb is that the smaller the footprint, the smaller the equivalent series inductance (ESL). A look at the capacitor datasheets will enable you to verify this easily. It must be noted, however, that I have not seen many application notes that describe the optimal way to route the bypass capacitor. In addition, I have not come notfoundn any application notes that explain why routing A is better than routing B. As I usually do, I will explain what I mean with an example to help you understand. I have made a drawing that I would like you to see. Accordingly, the smaller the loop we create and the smaller the ESL, the more you would agree with what we studied at school or university. It is clear from these numbers that the capacitor at the top layer has a lower ESL than lower the capacitor at the bottom layer, because the distance between the capacitor and the VDD/GND layers is smaller than the distance between the capacitor at and the VDD/GND layers. Moreover, you will see that routing the vias on the pad side is better than routing them on the edge (we make the loop smaller by routing them on the pad side). Therefore, it can be said that ESL is largely determined by the following factors: There is also the physical dimension of the via (which is not discussed in this article) In relation to the pads, the position of the via is critical. GND/Vdd plane distance (the longer the distance, the worse it is) I hope you enjoyed it! Bye now!
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