Let's learn how to fix emissions due to clock lines.
Over the course of my career, I have helped many companies resolve EMC issues. One of the most common causes of failing EMC (but hard to fix if you don't know what to do) is due to the clock line.
For example, some MCUs require interfaces to some SDRAM memory.
The MCU and SDRAM will have some interface, and there will be a clock on one of the tracks.
In my experience, people often copy a reference design and follow design guidelines without fully understanding why those guidelines exist.
Those guidline might be able to improve the propagation delay difference between different signals if you are adjusting the trace length of all the traces for all the signals. In spite of this fact, it does not guarantee that you will not emit excessive amounts of RE.
It is important to realize that, even when the trace impedance is controlled and your ground plane is in a solid state, it still is not enough to guarantee low emissions.
In order to be sure that you are passing RE, you will need to do more than just that.
The purpose of this article is to give you an overview of what you need to know in order to maximize your chances of passing the EMC exam.
Hypotheses:
Layout with a solid ground plane behind all the traces (data, control, and clock) with a perfect layout.
The lengths are perfectly matched.
MCUs provide the clock.
So... we have an ideal scenario... and still failing EMC.
Clock fanout vs data and command fanout
A thing that is written in the datasheet, although it might not be obvious is that the fanout of the pin for the clock (from the MCU) is usually higher than the fanout of other pins. Consequently, these pins usually have a rise and fall time that is much shorter than the rise and fall time associated with data and control lines. As a result of this detail there will be a significant impact on the emission result. In fact, even if you have a very short line, you may be able to emit quite a bit (enough to fail EMC).
So... we should try to remember that the rise and fall time on clock line is so small that usually it creates emissions.
Having said that, let's learn three things now that we know that.
Identification of clock emissions
Fixing emission on even harmonics
Fixing emissions on odd harmonics
I believe that I have explained the above in a previous post, however, since (just this year) I have seen this happen a few times, I want to make sure that is going to be cristallin clear, how to fix and how to avoid.
Identification of clock emissions
Emission due to clock line are only narrow band and (an integer) multiple of the clock frequency.
for example if we have a 50 MHz clock and we wee some emission at 150 MHz and 250 MHz, we can assume that the emissions are coming from the clock.
Please notice that I have used the word narrowband. see the following drawing for clarification.
An EMC testing lab will provide you with some graphs like this one when you do a RE scan.
The above diagram shows that we are above the limits in three places.
In two points (150 MHz and 250 MHz), we have narrowband emissions, and in one area, we have some sort of wideband emissions.
Narrowband emissions are usually provided by the EMC lab with their exact frequency. For example, if you have peaks at 150 MHz and 250 MHz, the EMC lab will provide you with that information.
Once you have this information. Here's what you do:
250 MHz / 50 MHz = 5 => odd harmonic
150 MHz / 50 MHz = 3 => odd harmonic
The scan revealed that our clock emits two emissions on the third and fifth harmonics.
Now let's fix it.
To learn how I fix emissions from a clock line, we need to do a step back and
Why do we have odd and even harmonis?
An ideal squarewave (duty cycle 50 %) is rich of odd harmonic.
in an ideal scenarion, where there is no reflection on the clock line and the clock line is a fast rise time and fall time ,we should expect from the spectrum a large amount of odd harmonics.
However, as soon we have a reflection, some of the waveform get bounced back from the SDRAM to the MCU (or the clock driver), and the waveform will start to look like this instead:
The fact that we have reflection means that the squarewave is goind to look like the one in the above drawing, and that will create some even harmonics.
Therefore...
Therefore we can state that odd harminics are due to the fact that our driver has a very short rise time and fall time. This cause some reflection, and as result we also have even harmonics irradiated in the space.
How do I fix this?
In this case, I have my own solution.
The odd harmonics are caused by the clock's sharp edges, as I have explained above. We may be able to reduce the amplitude of odd harmonics just enough in order to pass EMC if we tune these edges (from just a few psec) over a short time period.
As a result. At the source of a clock line, I suggest adding a do not fit capacitor. In the stage when you are designing the board, at that point, you are not sure if you will have problems during the EMC testing . Nevertheless, it is advisable to leave some space in the space for a capacitor that may make the difference between the test passing or failing. In other words, if you do not need it, then you will fit it.
In order to fix even harmonics, I usually use a small resistor placed shortly after the capacitor in order to fix them.
By using the resistor, we are able to reduce the overvoltage peak at the SDRAM side, which in our example is causing the emissions to occur due to the overvoltage peak.
As a result, the above solution has helped me to solve a wide variety of problems. This method has worked very well for me, and I hope I have been able to convey this information to you.
It is important not to use a RC low pass filter, but a CR one.
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