These days, we tend to encounter circuits with microcontrollers that incorporate AD/DA converters as a part of their design. As an example, Infineon has a very powerful PSoC with integrated digital blocks, operational amplifiers, etc., which is one of the most powerful PSoCs on the market today, I think. It's almost like having a whole System on Chip, with a small FPGA, a few operational amplifiers, analog multiplexers, AD and DA circuits, etc. You can also create a Verilog digital block if you can't find the block you need in their library. So overall, it's a very complex IC.
The solutions I have designed with PSoC have been very complex. For example, I have designed PID controllers, Class D digital sinewave generators, analog PLLs, MPTT and so on.
When use digital and analog within the same chip, it is important to minimize any noise from the Analog Power pins VADD.
This is the first question we should ask ourselves. How do you interpret noise from an analog circuit?
In the analog bandwidth range, any differential voltage between AVDD and GND (see FIG.1) can be considered noise.
Take a look at FIG.1. There's no filter between analog and digital.
As you can see the AVDD will also be noisy if the GND is "noisy".
FIG.1 the GND "noise" is "seen" from the AVDD pin
It's hard to have a noiseless GND in a mixed signal design. I've written several articles on how to control AC and DC current. There's still a lot to be done to minimize noise between AVDD and GND.
Imagine for a minute if we could inject all the noise from the DGND onto the Analog VDD.
In DC we have that VDD = AVDD (for example 3.3V), but in AC, or within the analog bandwidth we're interested in, any voltage on GND is also present at AVDD.
As you can see in this case, the chip does not see any noise between the Analog power pin and the GND pin.
Nevertheless, what is important to note is that what we have done is that we have injected noise from the GND to the AVDD. This can be seen in FIG.2.
FIG.2 the GND noise is now reduced, since it has been injected on the AVDD pin.
Here's a very simplistic analysis of FIG.2.
In DC, the inductor is a short and the capacitor is an open circuit, so AVDD(0 Hz) = DVDD(0 Hz).
At high frequency, the inductor has an open circuit and the capacitor has a short circuit. All the HF noise coming from GND will be injected into AVDD through capacitor C.
Since we can't eliminate the noise from the GND, what we do is we inject the same noise into the Analog power pin VDD. This way the differential noise between AVDD and GND is as low as possible.
This technique is very common these days, and you might see it recommended in many application notes.
However, I think most application notes don't explain how this circuit actually works.
This trick works very well in improving Conductive immunity on a mixed IC as well!
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